The present invention relates to a semiconductor memory device, and more particularly to a technology of reducing a number of address pins used to test it.
As is well known in the art, a semiconductor memory device manufactured by a series of processes operates in response to addresses, power, commands, data, etc. inputted from outside, as defined in JEDEC (Joint Electron Device Engineering Council). Here, the addresses are classified into bank addresses for designating each of banks and normal addresses. The banks are equal-sized parts into which an area where data cells of the semiconductor memory device coexist is divided for efficient operation of data. There are various numbers of banks such as 4 or 8 banks depending on the size of a chip.
FIG. 1 is a block diagram showing the connection of address channels between test equipment and a semiconductor memory device on the existing test.
Addresses are inputted from the test equipment to the semiconductor memory device during test. For convenience of explanation, it is assumed that there are 2 bank addresses and 13 normal addresses.
Meanwhile, a line connected between the test equipment and the semiconductor memory device is called a channel. If the addresses are given as above, the test equipment should assign 15 address channels to each semiconductor memory device. FIG. 1 shows a case where 128 memory devices are tested simultaneously. In this case, the test equipment must have 1920 address channels.
FIG. 2 is a block diagram illustrating the arrangement of address channels to address pads on the existing test.
As shown in the drawing, 15 addresses A1 to A15 are inputted from the test equipment to the memory device as 2 bank addresses BA0 and BA1 and 13 normal addresses NA0 to NA12. Based on the addresses so inputted, the memory device writes/reads data in/from desired addresses.
As is well known in the art, the test is a very important process in manufacturing the semiconductor memory device and test time is directly related to manufacturing costs. The test of the semiconductor memory device is performed by applying various signals thereto through the test equipment. However, the number of channels in the test equipment is limited. Thus, the decrease in the number of channels required for testing is an important issue in the semiconductor memory device.
In other words, the more the number of channels (or pins) required for test is decreased, the greater the number of chips can be tested at a time by the same equipment. This reduces the test time as well as manufacturing costs.